SystemVerilog struct assignment

You may have occasion to initialize a structure in SystemVerilog:

typedef struct {
    int f1;
    int f2;
    int f3;
} set_of_values_T;

set_of_values_T set_of_values = {1, 2, -3};

This might seem fine, but the above assignment is actually a concatenation. The simulator will take the set of values and pack them into one big bit vector.

In my experience, Modelsim was okay with positive values, or a mix of positive and negative values. In compilation, it would note that it was promoting an assignment to a concatenation. But if all the values were negative, it would give an error that a packed value was being assigned to an unpacked value.

A quick Google search turned up a book preview that showed an example of how to initialize a structure. Very simple, really. Just add a tick (') before the assignment:

set_of_values_T set_of_values = '{1, 2, 3};

This does the trick, and the notes and errors go away. SystemVerilog uses the '{} construct to differentiate a list of values from a concatenation, {}.

EDIT: Another example, this time with a dynamic array or queue:

bit [0:2] values[$]= '{3,5,6};